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CY7C1360A CY7C1362A
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM
Features
* * * * * * * * * * * * * * * * * * Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V -5% and +10% power supply 3.3V or 2.5V I/O supply 5V-tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Multiple chip enables for depth expansion: three chip enables for A package version and two chip enables for BG and AJ package versions Address pipeline capability Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down feature available using ZZ mode or CE deselect JTAG boundary scan for BG and AJ package version Low-profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid Array) and 100-pin TQFP packages synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and BWE), and global Write (GW). However, the CE3 chip enable input is only available for the TA package version. Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV). Address, data inputs, and Write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the Write control inputs. Individual byte Write allows individual byte to be written. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. BWa, BWb, BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The x18 version only has 18 data inputs/outputs (DQa and DQb) along with BWa and BWb (no BWc, BWd, DQc, and DQd). For the B and T package versions, four pins are used to implement JTAG test capabilities: Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The TA package version does not offer the JTAG capability. The CY7C1360A and CY7C1362A operate from a +3.3V power supply. All inputs and outputs are LVTTL-compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs integrate 262,144 x 36 and 524,288 x 18 SRAM cells with advanced
Selection Guide
7C1360A-225 7C1362A-225 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.5 650 10 7C1360A-200 7C1362A-200 3.0 620 10 7C1360A-166 7C1362A-166 3.5 530 10 7C1360A-150 7C1362A-150 3.5 480 10 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05258 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 * 408-943-2600 Revised May 24, 2002
CY7C1360A CY7C1362A
Functional Block Diagram--256K x 36[1]
BWa BWa BWE BWE CLK CLK BWb BWb GW GW
BYTE c WRITE BYTE a WRITE
D
Q
BYTE b WRITE
D
Q
BWc BWc
D
Q
BYTE d WRITE
BWd BWd
D
Q
byte d write byte c write Output Buffers byte b write byte a write
CE1 CE CE2 CE2 CE3 CE2 OE OE ZZ ZZ ADSP ADSP AA ADSC ADSC
CLR
16
ENABLE
D
Q
D
Q
Power Down Logic Input Register
Address Register 256K x 9 x 4 SRAM Array
OUTPUT REGISTER
D
Q
DQa, DQb, DQa,DQb DQc, DQd DQc,DQd
ADV ADV A0-A1 A1-A0
MODE MODE
Binary Counter & Logic
Functional Block Diagram--512K x 18[1]
BWbBWb BWE BWE CLK
BYTE a WRITE BYTE b WRITE
D
Q
BWaBWa GW GW
D
Q
byte a write byte b write Output Buffers
CE1 CE CE2 CE2 CE3CE2 ZZ
ZZ Power Down Logic
ENABLE
D
Q
D
Q
OE OE ADSP ADSP
Input Register
17
A
A
Address Register 512K x 9 x 2 SRAM Array
ADSC ADSC
CLR
OUTPUT REGISTER
D
Q
DQa, DQb, DQa,DQb
ADV ADV
A1-A0 A0-A1 MODE MODE
Binary Counter & Logic
Notes: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information. 2. CE3 is for TA version only.
Document #: 38-05258 Rev. *A
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CY7C1360A CY7C1362A
Pin Configurations
CY7C1360A 256K x 36 100-pin TQFP Top View
DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc NC VCC NC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A CE CE2 BWd BWc BWb BWa A VCC VSS CLK GW BWE OE ADSC ADSP ADV A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE CE2 BWd BWc BWb BWa CE3 VCC VSS CLK GW BWE OE ADSC ADSP ADV A A
DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc NC VCC NC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP T Version
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa
100-pin TQFP TA Version
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A
CY7C1362A 512K x 18 100-pin TQFP Top View
A NC NC VCCQ VSS NC DPa DQa DQa VSS VCCQ DQa DQa VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VDDQ NC NC NC NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb NC VCC NC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A CE CE2 NC NC BWb BWa A VCC VSS CLK GW BWE OE ADSC ADSP ADV A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE CE2 NC NC BWb BWa CE3 VCC VSS CLK GW BWE OE ADSC ADSP ADV A A
MODE A A A A A1 A0 NC NC VSS VCC NC A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb NC VCC NC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP T Version
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100-pin TQFP TA Version
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VCCQ VSS NC DQa DQa DQa VSS VCCQ DQa DQa VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VCCQ NC NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Document #: 38-05258 Rev. *A
MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A
MODE A A A A A1 A0 NC NC VSS VCC NC A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1360A CY7C1362A
Pin Configurations (continued)
CY7C1360A 256K x 36 119-ball BGA Top View 1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQc DQc VCCQ DQc DQc VCCQ DQd DQd VCCQ DQd DQd NC NC VCCQ 2 A CE2 A DQc DQc DQc DQc DQc VCC DQd DQd DQd DQd DQd A NC TMS 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI 4 ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC A TCK 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQb DQb DQb DQb DQb VCC DQa DQa DQa DQa DQa A NC NC 7 VCCQ NC NC DQb DQb VCCQ DQb DQb VCCQ DQa DQa VCCQ DQa DQa NC ZZ VCCQ
CY7C1362A 512K x 18 119-ball BGA Top View 1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQb NC VCCQ NC DQb VCCQ NC DQb VCCQ DQb NC NC NC VCCQ 2 A CE2 A NC DQb NC DQb NC VCC DQb NC DQb NC DQb A A TMS 3 A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC NC TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A CE3 A DQa NC DQa NC DQa VCC NC DQa NC DQa NC A A NC 7 VCCQ NC NC NC DQa VCCQ DQa NC VCCQ DQa NC VCCQ NC DQa NC ZZ VCCQ
Document #: 38-05258 Rev. *A
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CY7C1360A CY7C1362A
256K x 36 Pin Descriptions
X36 PBGA Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 2R, 6R, 3T, 4T, 5T X36 QFP Pins Name Type InputSynchronous Description Addresses: These inputs are registered and must meet the set-up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. 37 A0 36 A1 35, 34, 33, 32, 100, A 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 92 (T/AJ Version) 43 (TA/A Version) 93 94 95 96 87 BWa BWb BWc BWd BWE
5L 5G 3G 3L 4M
InputSynchronous
Byte Write: A byte Write is LOW for a Write cycle and HIGH for a Read cycle. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. Write Enable: This active LOW input gates byte Write operations and must meet the set-up and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 36-bit Write to occur independent of the BWE and BWn lines and must meet the set-up and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, Write control, and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP. Chip Enable: This active HIGH input is used to enable the device. Chip Enable: This active LOW input is used to enable the device. Not available for B and T package versions. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. Address Status Controller: This active LOW input causes the device to be deselected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon Write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst.
InputSynchronous InputSynchronous
4H
88
GW
4K
89
CLK
InputSynchronous
4E 2B - (not available for PBGA) 4F 4G
98 97 92 (for TA/A version only) 86 83
CE CE2 CE3
InputSynchronous InputSynchronous InputSynchronous Input InputSynchronous InputSynchronous
OE ADV
4A
84
ADSP
4B
85
ADSC
InputSynchronous
3R
31
MODE
InputStatic
7T
64
ZZ
InputSleep: This active HIGH input puts the device in low Asynchronous power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect).
Document #: 38-05258 Rev. *A
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CY7C1360A CY7C1362A
256K x 36 Pin Descriptions (continued)
X36 PBGA Pins (a) 6P, 7P, 7N, 6N, 6M, 6L, 7L, 6K, 7K, (b) 7H, 6H, 7G, 6G, 6F, 6E, 7E, 7D, 6D, (c) 2D, 1D, 1E, 2E, 2F, 1G, 2G, 1H, 2H, (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 2U 3U 4U X36 QFP Pins (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 Name DQa DQb DQc DQd Type Input/ Output Description Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb. Third Byte is DQc. Fourth Byte is DQd. Input data must meet set-up and hold times around the rising edge of CLK.
38 TMS 39 TDI 43 TCK for BG/B and T/AJ version 42 TDO for BG/B and T/AJ version 15, 41, 65, 91 VCC
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for TA/A package version.
5U
Output
IEEE 1149.1 test output. LVTTL-level output. Not available for TA package version.
4C, 2J, 4J, 6J, 4R
Power Supply Core power supply: +3.3V -5% and +10% Ground Ground: GND.
3D, 5D, 3E, 5E, 3F, 5F, 5, 10, 17, 21, 26, VSS 3H, 5H, 3K, 5K, 3M, 40, 55, 60, 67, 71, 5M, 3N, 5N, 3P, 5P 76, 90 1A, 7A, 1F, 7F, 1J, 7J, 4, 11, 20, 27, 54, 1M, 7M, 1U, 7U 61, 70, 77 VCCQ
I/O Power Supply -
Power Supply for the I/O circuitry No Connect: These signals are not internally connected. User can leave it floating or connect it to VCC or VSS.
1B, 7B, 1C, 7C, 4D, 3J, 14, 16, 66 NC 5J, 4L, 1R, 5R, 7R, 1T, 38, 39, 42 for TA/A 2T, 6T, 6U version
512K x 18 Pin Descriptions
X18 PBGA Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T X18 QFP Pins Name Type InputSynchronous Description Addresses: These inputs are registered and must meet the set up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. 37 A0 36 A1 35, 34, 33, 32, 100, A 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 92 (T/AJ Version) 43 (TA/A Version) 93 94 BWa BWb
5L 3G
InputSynchronous
Byte Write Enables: A byte Write enable is LOW for a Write cycle and HIGH for a Read cycle. BWa controls DQa. BWb controls DQb. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. Write Enable: This active LOW input gates byte Write operations and must meet the set-up and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-bit Write to occur independent of the BWE and WEn lines and must meet the set-up and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, Write control and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP. Chip Enable: This active HIGH input is used to enable the device. Page 6 of 28
4M
87
BWE
InputSynchronous InputSynchronous
4H
88
GW
4K
89
CLK
InputSynchronous
4E 2B
98 97
CE CE2
InputSynchronous InputSynchronous
Document #: 38-05258 Rev. *A
CY7C1360A CY7C1362A
512K x 18 Pin Descriptions (continued)
X18 PBGA Pins - (not available for PBGA) 4F 4G X18 QFP Pins 92 (for TA/A Version only) 86 83 Name CE3 Type InputSynchronous Input InputSynchronous InputSynchronous Description Chip Enable: This active LOW input is used to enable the device. Not available for BG/B and T/AJ package versions. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon Write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. An NC or HIGH on this pin selects Interleaved Burst.
OE ADV
4A
84
ADSP
4B
85
ADSC
InputSynchronous
3R
31
MODE
InputStatic
7T
64
ZZ
InputSleep: This active HIGH input puts the device in low power Asynchronous consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). Input/ Output Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb. Input data must meet set up and hold times around the rising edge of CLK. IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for TA/A package version.
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 2U 3U 4U 5U
(a) 58, 59, 62, 63, DQa 68, 69, 72, 73, 74 DQb (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 38 TMS 39 TDI 43 TCK for B and T version 42 TDO for BG/B and T/AJ version 15, 41,65, 91 VCC 5, 10, 17, 21, 26, VSS 40, 55, 60, 67, 71, 76, 90 VCCQ
Input
Output
IEEE 1149.1 test output. LVTTL-level output. Not available for TA/A package version. Core power supply: +3.3V -5% and +10% Ground: GND.
4C, 2J, 4J, 6J, 4R 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P
Supply Ground
1A, 7A, 1F, 7F, 1J, 7J, 4, 11, 20, 27, 54, 1M, 7M, 1U, 7U 61, 70, 77 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T, 6U
I/O Power Supply -
Power Supply for the I/O circuitry No Connect: These signals are not internally connected. User can leave it floating or connect it to VCC or VSS.
1-3, 6, 7, 14, 16, NC 25, 28-30, 51-53, 56, 57, 66, 75, 78, 79, 80, 95, 96 38, 39, 42 for TA Version
Document #: 38-05258 Rev. *A
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CY7C1360A CY7C1362A
Introduction
Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.8 ns (133-MHz device). The CY7C1360A/CY7C1362A supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWa,b,c,d for 1360A and BWa,b for 1362A) inputs. A Global Write Enable (GW) overrides all byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for BGA) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the Write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within preliminary ns (200-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the RAM core. The Write signals (GW, BWE, and BWx) and ADV inputs are ignored during this first cycle. ADSP triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the Write operation is controlled by BWE and BWx signals. The CY7C1360A/CY7C1362A provides byte Write capability that is described in the Write cycle description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWa,b,c,d for CY7C1360A and BWa,b for CY7C1362A) input will selectively write to only the desired bytes. Bytes not selected during a byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1360A/CY7C1362A is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQ are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BWx) are asserted active to conduct a Write to the desired byte(s). ADSC triggered Write accesses require a single clock cycle to complete. The address presented to A[17:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQ[x:0] is written into the corresponding address location in the RAM core. If a byte Write is conducted, only the selected bytes are written. Bytes not selected during a byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1360A/CY7C1362A is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ[x:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[x:0] are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1360A/CY7C1362A provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel(R) Pentium(R) applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported.
Document #: 38-05258 Rev. *A
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CY7C1360A CY7C1362A
Burst Address Table (MODE = NC/VCC)
First Address (external) A[1:0]] 00 01 10 11 Second Address (internal) A[1:0] 01 00 11 10 Third Address (internal) A[1:0] 10 11 00 01 Fourth Address (internal) A[1:0] 11 10 01 00
Burst Address Table (MODE = GND)
First Address (external) A[1:0]] 00 01 10 11 Second Address (internal) A[1:0] 01 10 11 00 Third Address (internal) A[1:0] 10 11 00 01 11 00 01 10 Fourth Address (internal) A[1:0]
Truth Table[3, 4, 5, 6, 7, 8, 9]
Next Cycle Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write ZZ "sleep" Address Used ZZ None None None None None External External Next Next Next Next Current Current Current Current Current Current External Next Next Current Current None O O O O O O O O O O O O O O O O O O O O O O 1 CE3 X 1 X 1 X 0 0 X X X X X X X X X X 0 X X X X X CE2 X X 0 X 0 1 1 X X X X X X X X X X 1 X X X X X CE1 ADSP ADSC ADV 1 0 0 0 0 0 0 X X 1 1 X X 1 1 X 1 0 X 1 X 1 X X 0 0 1 1 0 1 1 1 X X 1 1 X X 1 X 1 1 X 1 X X 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 X X X X X X X X 0 0 0 0 1 1 1 1 1 1 X 0 0 1 1 X OE X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z X X X X X X Read Read Read Read Read Read Read Read Read Write Write Write Write Write Write Write X DQ
Notes: 3. X = "Don't Care." H = logic HIGH. L = logic LOW. For X36 product, Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH. For X18 product, Write = L means [BWE + BWa*BWb]*GW equals LOW. Write = H means [BWE + BWa*BWb]*GW equals HIGH. 4. BWa enables Write to DQa. BWb enables Write to DQb. BWc enables Write to DQc. BWd enables Write to DQd. 5. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 6. Suspending burst generates wait cycle.l 7. For a Write operation following a Read operation, OE must be HIGH before the input-data-required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 9. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
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Partial Truth Table for Read/Write[10]
Function (1360A) Read Read Write Byte 0 - DQa Write Byte 1 - DQb Write Bytes 1, 0 Write Byte 2 - DQc Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 - DQd Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes Write All Bytes Function (1362A) Read Read Write Byte 0 - DQ[7:0] and DP0 Write Byte 1 - DQ[15:8] and DP1 Write All Bytes Write All Bytes Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. GW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 BWE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X GW 1 1 1 1 1 0 BWd X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X BWE 1 0 0 0 0 X BWc X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X BWb X 1 1 0 0 X BWb X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 X BWa X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X BWa X 1 0 1 0 X
Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS Description Sleep mode standby current Device operation to ZZ Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V 2tCYC Min. Max. 10 2tCYC Unit mA ns ns
tZZREC ZZ recovery time Note: 10. For the X18 product, there are only BWa and BWb.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview This device incorporates a serial boundary scan access port (TAP). This port is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1-compliant TAPs. The TAP operates using LVTTL/ LVCMOS logic level signaling. Disabling the JTAG Feature It is possible to use this device without using the JTAG feature. To disable the TAP controller without interfering with normal operation of the device, TCK should be tied LOW (VSS) to prevent clocking the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be pulled up to VCC through a resistor. TDO should be left unconnected. Upon power-up the device will come up in a reset state which will not interfere with the operation of the device. Performing a TAP Reset The TAP circuitry does not have a reset pin (TRST, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (VCC) for five rising edges of TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. At power-up, the TAP is reset internally to ensure that TDO is in a High-Z state.
TAP Registers
Overview The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected, it is connected between the TDI and TDO pins. Instruction Register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction upon power-up or whenever the controller is placed in the test-logic reset state. When the TAP controller is in the Capture-IR state, the two LSBs of the serial instruction register are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. Bypass Register The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The Boundary Scan register is connected to all the input and bidirectional I/O pins (not counting the TAP pins) on the device. This also includes a number of NC pins that are reserved for future needs. There are a total of 70 bits for the x36 device and 51 bits for the x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the device I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order table describes the order in which the bits are connected. The first column defines the bit's position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name, the third column is the TQFP pin number, and the fourth column is the BGA bump number.
Test Access Port
TCK-Test Clock (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS-Test Mode Select (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. TDI-Test Data In (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 1, TAP Controller State Diagram). It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up internally, resulting in a logic HIGH level. TDI is connected to the Most Significant Bit (MSB) of any register (see Figure 2.). TDO-Test Data Out (OUTPUT) The TDO output pin is used to serially clock data-out from the registers. The output that is active depending on the state of the TAP state machine (refer to Figure 1, TAP Controller State Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the Least Significant Bit (LSB) of any register (see Figure 2.).
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Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the device as described in the Identification Register Definitions table. and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power-up and at any time the TAP controller is placed in the test-logic reset state. SAMPLE-Z If the High-Z instruction is loaded in the instruction register, all output pins are forced to a High-Z state and the boundary scan register is connected between TDI and TDO pins when the TAP controller is in a Shift-DR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction. The PRELOAD portion of the command is not implemented in this device, so the device TAP controller is not fully IEEE 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR state, a snap shot of the data in the device's input and I/O buffers is loaded into the boundary scan register. Because the device system clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the input and I/O ring contents while the buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. To guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the TAP controller's capture set up plus hold time (tCS plus tCH). The device clock input(s) need not be paused for any other TAP operation except capturing the input and I/O ring contents into the boundary scan register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use.
TAP Controller Instruction Set
Overview There are two classes of instructions defined in IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows IEEE 1149.1 conventions, it is not IEEE 1149.1-compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the device or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction sets for this device are listed in the following tables. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this device. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the device responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places the device outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI
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1
TEST-LOGIC RESET 0 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 1 0
0
REUN-TEST/ IDLE
1
SELECT DR-SCAN 0 1
1
Figure 1. TAP Controller State Diagram[11]
Note: 11. The "0"/"1" next to each state represents the value at TMS at the rising edge of TCK.
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0 Bypass Register Selection Circuitry TDI Selection Circuitry TDO
2 Instruction Register
1
0
31 30
29
.
.
2
1
0
Identification Register
x
.
.
.
.
2
1
0
Boundary Scan Register [12]
TDI TAP Controller TDI
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics (20C < Tj < 110C; VCC = 3.3V -0.2V and +0.3V unless otherwise noted)
Parameter VIH VIl ILI ILI ILO VOLC VOHC VOLT VOHT Description Input High (Logic 1) Voltage Input Leakage Current TMS and TDI Input Leakage Current Output Leakage Current LVCMOS Output Low Voltage[13, 15] LVCMOS Output High Voltage LVTTL Output Low Voltage
[13] [13, 15] [13, 14]
Test Conditions
Min. 2.0 -0.3
Max. VCC + 0.3 0.8 5.0 30 5.0 0.2
Unit V V A A A V V V V
Input Low (Logic 0) Voltage[13, 14] 0V < VIN < VCC 0V < VIN < VCC Output disabled, 0V < VIN < VCCQ IOLC = 100 A IOHC = 100 A IOLT = 8.0 mA IOHT = 8.0 mA
-5.0 -30 -5.0
VCC - 0.2 0.4 2.4
LVTTL Output High Voltage[13]
Notes: 12. X = 69 for the x36 configuration; X = 50 for the x18 configuration. 13. All voltage referenced to VSS (GND). 14. Overshoot: VIH(AC) < VCC + 1.5V for t < tKHKH/2; undershoot: VIL(AC) < - 0.5V for t < tKHKH/2; power-up: VIH < 3.6V and VCC < 3.135V and VCCQ < 1.4V for t < 200 ms. During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than tKHKL (min.). 15. This parameter is sampled.
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TAP AC Switching Characteristics Over the Operating Range[16, 17]
Parameter Clock tTHTH fTF tTHTL tTLTH Output Times tTLQX tTLQV tDVTH tTHDX Set-up Times tMVTH tTDIS tCS Hold Times tTHMX tTDIH tCH TMS Hold TDI Hold after Clock Rise Capture Hold 5 5 5 ns ns ns TMS Set-up TDI Set-up to TCK Clock Rise Capture Set-up 5 5 5 ns ns ns TCK LOW to TDO Unknown TCK LOW to TDO Valid TDI Valid to TCK HIGH TCK HIGH to TDI Invalid 5 5 0 10 ns ns ns ns Clock Cycle Time Clock Frequency Clock HIGH Time Clock LOW Time 8 8 20 50 ns MHz ns ns Description Min. Max. Unit
Notes: 16. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 17. Test conditions are specified using the load in TAP AC test conditions.
TAP Timing and Test Conditions
TDO Z0 = 50 50 50 50 Vt = 1.5V 20 pF
ALL INPUT PULSES 3.0V 1.5V VSS 1.5 ns
(a)
tTHTH t
(b)
THTL
t
1.5 ns
TLTH
TEST CLOCK (TCK)
tMVTH tTHMX
TEST MODE SELECT (TMS)
tDVTH tTHDX
TEST DATA IN (TDI)
t t
TLQV
TLQX
TEST DATA OUT (TDO)
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Identification Register Definitions
Instruction Field Revision Number (31:28) Device Depth (27:23) Device Width (22:18) Reserved (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) 256K x 36 XXXX 00110 00100 XXXXXX 00011100100 1 512K x 18 XXXX 00111 00011 XXXXXX 00011100100 1 Description Reserved for revision number. Defines depth of 256K or 512K words. Defines width of x36 or x18 bits. Reserved for future use. Allows unique identification of DEVICE vendor. Indicates the presence of an ID register.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size (x36) 3 1 32 70 Bit Size (x18) 3 1 32 51
Instruction Codes
Instruction EXTEST Code 000 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. This instruction is not IEEE 1149.1-compliant. Preloads ID register with vendor ID code and places it between TDI and TDO. This instruction does not affect device operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. Do not use these instructions; they are reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This instruction does not affect device operations. This instruction does not implement IEEE 1149.1 PRELOAD function and is therefore not 1149.1-compliant. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Places the bypass register between TDI and TDO. This instruction does not affect device operations.
IDCODE SAMPLE-Z RESERVED SAMPLE/PRELOAD
001 010 011 100
RESERVED RESERVED BYPASS
101 110 111
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Boundary Scan Order (256K x 36)
Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name A A A A A A A DQa DQa DQa DQa DQa DQa DQa DQa DQa ZZ DQb DQb DQb DQb DQb DQb DQb DQb DQb A A ADV ADSP ADSC OE BWE GW CLK TQFP 44 45 46 47 48 49 50 51 52 53 56 57 58 59 62 63 64 68 69 72 73 74 75 78 79 80 81 82 83 84 85 86 87 88 89 Bump ID 2R 3T 4T 5T 6R 3B 5B 6P 7N 6M 7L 6K 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 7H 6G 6E 7D 6A 5A 4G 4A 4B 4F 4M 4H 4K
Boundary Scan Order (256K x 36) (continued)
Bit# 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Name A BWa BWb BWc BWd CE2 CE A A DQc DQc DQc DQc DQc DQc DQc DQc DQc NC DQd DQd DQd DQd DQd DQd DQd DQd DQd MODE A A A A A1 A0 TQFP 92 93 94 95 96 97 98 99 100 1 2 3 6 7 8 9 12 13 14 18 19 22 23 24 25 28 29 30 31 32 33 34 35 36 37 Bump ID 6B 5L 5G 3G 3L 2B 4E 3A 2A 2D 1E 2F 1G 2H 1D 2E 2G 1H 5R 2K 1L 2M 1N 2P 1K 2L 2N 1P 3R 2C 3C 5C 6C 4N 4P
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Boundary Scan Order (512K x 18)
Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal Name A A A A A A A DQa DQa DQa DQa ZZ DQa DQa DQa DQa DQa A A A ADV ADSP ADSC OE BWE GW TQFP 44 45 46 47 48 49 50 58 59 62 63 64 68 69 72 73 74 80 81 82 83 84 85 86 87 88 Bump ID 2R 2T 3T 5T 6R 3B 5B 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 6T 6A 5A 4G 4A 4B 4F 4M 4H
Boundary Scan Order (512K x 18) (continued)
Bit# 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal Name CLK A BWa BWb CE2 CE A A DQb DQb DQb DQb NC DQb DQb DQb DQb DQb MODE A A A A A1 A0 TQFP 89 92 93 94 97 98 99 100 8 9 12 13 14 18 19 22 23 24 31 32 33 34 35 36 37 Bump ID 4K 6B 5L 3G 2B 4E 3A 2A 1D 2E 2G 1H 5R 2K 1L 2M 1N 2P 3R 2C 3C 5C 6C 4N 4P
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Voltage on VCC Supply Relative to VSS[19] .... -0.5V to +4.6V VIN ................................................................... -0.5V to 5.5V Storage Temperature (plastic) ...................... -55C to +150 Junction Temperature ..................................................+150 Power Dissipation .........................................................1.0W Short Circuit Output Current ........................................ 50 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature[18] VCC[19] VCCQ Commercial 0C to +70C 3.3V 2.5V - 5/ -5/+10 Industrial -40C to +85C 3.3V + 10% %
Electrical Characteristics Over the Operating Range
Parameter VIHD VIH VIL ILI ILI ILO VOH VOL VCC[19] VCCQ Description Input High (Logic 1) Voltage[13, 20] Test Conditions All other inputs 3.3V I/O 2.5V I/O 3.3V I/O 2.5V I/O 0V < VIN < VCC 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -5.0 mA for 3.3V I/O IOH = -1.0 mA for 2.5V I/O IOL = 8.0 mA for 3.3V I/O IOL = 1.0 mA for 2.5V I/O 3.3V I/O 2.5V I/O Min. 2.0 2.0 1.7 -0.3 -0.3 2.4 2.0 Max. VCC + 0.3 Unit V V V V V A A A V V V V V V V
Input Low (Logic 0) Voltage[13, 20] Input Leakage Current MODE and ZZ Input Leakage Current[21] Output Leakage Current Output High Voltage[13] Output Low Voltage[13] Supply Voltage[13] I/O Supply Voltage[13]
0.8 0.7 5 30 5
3.135 3.135 2.375
0.4 0.4 3.63 3.63 2.9
Parameter Description VCC Operating Supply[22, 23, 24] ICC
ISB1
Automatic CE Power-down Current--TTL Inputs[23, 24] Automatic CE Power-down Current--CMOS Inputs[23, 24] Automatic CE Power-down Current-- CMOS Inputs Automatic CS Power-down Current--TTL Inputs[23, 24]
ISB2
ISB3
ISB4
225 Conditions Typ. MHz Device selected; all inputs < VILor > VIH; 150 650 VCC = Max.; outputs open, f = f MAX = 1/tcyc. 150 350 Device deselected; all inputs < VIL or > VIH; VCC = Max.; f = f MAX = 1/tcyc. 5 10 Device deselected; VCC = Max.; all inputs < VSS + 0.2 or > VCC - 0.2; all inputs static; CLK frequency = 0 Max. VDD Device Deselected, or V IN < 90 260 0.3V or VIN > VDDQ -- 0.3V f = f MAX = 1/t CYC 15 30 Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max. CLK frequency = 0 Typ. 5 7
Max. 200 166 MHz MHz 620 530
150 MHz Unit 480 mA
300
265
225
mA
10
10
10
mA
230
200
180
mA
30
30
30
mA
Capacitance[15]
Parameter CI CI/O Description Test Conditions Input Capacitance TA = 25C, f = 1 MHz, Input/Output Capacitance (DQ) VCC = 3.3V Max. 7 8 Unit pF pF
Notes: 18. TA is the case temperature. 19. The ground level at the start of "power on" on the VCC pins should be no greater than 200mV. 20. Overshoot: VIH < + 6.0V for t < tKC /2; undershoot:VIL < -2.0V for t < tKC /2. 21. Output loading is specified with CL=5 pF as in AC Test Loads. 22. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 23. "Device Deselected" means the device is in Power-Down mode as defined in the truth table. "Device Selected" means the device is active. 24. Typical values are measured at 3.3V, 25C, and 20 ns cycle time.
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Thermal Resistance[15]
Parameter JA JC Description Test Conditions TQFP Typ. 25 9 Unit C/W C/W Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch, 4-layer PCB Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms
OUTPUT Z0 = 50 RL = 50 VTH = 1.5V VCCQ OUTPUT 5 pF R = 351 INCLUDING JIG AND SCOPE R = 317 ALL INPUT PULSES VCCQ 10% GND 90% 90% 10%
1 V/ns
1 V/ns
(a)
(b)
(c)
Switching Characteristics Over the Operating Range[24]
225 MHz Parameter Clock tKC tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tS Hold Times tH Address, Controls, and Data In[28] 0.4 0.4 0.5 0.5 ns
Notes: 25. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted. 26. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 27. OE is a "Don't Care" when a byte Write enable is sampled LOW. 28. This is a synchronous device. All synchronous inputs must meet specified set up and hold time, except for "Don't Care" as defined in the truth table. 29. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. CE2 is only available for TA package version.
200 MHz Min. 5.0 2.0 2.0 Max.
166 MHz Min. 6.0 2.4 2.4 Max.
150 MHz Min. 6.7 2.6 2.6 Max. Unit ns ns ns 3.5 4.5 1.25 0 ns ns ns ns 4.0 3.5 4.5 0 3.5 2.0 ns ns ns ns ns ns
Description Clock Cycle Time Clock HIGH Time Clock LOW Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z OE to Output Valid[27] OE to Output in Low-Z
[15, 20, 26] [15, 20, 26]
Min. 4.4 1.8 1.8 VCCQ = 3.3V VCCQ = 2.5V 1.25 0 1.25
Max.
Output Times 2.8 2.8 1.25 0 3.0 2.8 2.8 0 2.8 1.4 1.4 0 3.0 1.5 1.25 2.6 3.0 3.0 0 3.5 3.1 3.1 1.25 0 1.0 2.8 3.5 4.0 3.5 4.0
Clock to Output in High-Z
1.25
VCCQ = 3.3V VCCQ = 2.5V
[15, 20, 26] [15, 20, 26]
OE to Output in High-Z
Set-up Times Address, Controls, and Data In[28]
Document #: 38-05258 Rev. *A
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CY7C1360A CY7C1362A
Switching Waveforms
Read Timing[29, 30]
tKC tKL
CLK CLK
tS tKH
ADSP ADSP
tH
ADSC ADSC
tS
A ADDRESS
A1
tH
A2
W BW a, BW b, x BW BW c, BWE d BW GW E, G W
CE CE
tS
tS
ADV ADV
tH
O E OE
tKQ
DQx DQ
tKQLZ
tOELZ
Q (A1)
tOEQ
tKQ
Q (A2) Q (A2+1) Q (A2+2) Q (A2+3) Q (A2) Q (A2+1)
SING READ LE
BURST READ
Note: 30. For the X18 product, there are only BWa and BWb for byte Write control.
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CY7C1360A CY7C1362A
Switching Waveforms (continued)
Write Timing[29, 30]
CLK CLK
tS
ADSP ADSP
tH
ADSC ADSC
tS
A ADDRESS
A1
tH
A2
A3
BW BW a, b, BW BWx c, BW d, BWE E BW
Chan
GW GW
CE CE
tS
ADV ADV
tH
OE OE
tOEHZ tKQX
DQx DQ
Q D(A1) D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2)
SINGLE W RITE
BURST W RITE
BURST W RITE
Document #: 38-05258 Rev. *A
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CY7C1360A CY7C1362A
Switching Waveforms (continued)
Read/Write Timing[29, 30]
CLK
CLK
tS
ADSP ADSP
tH
ADSC ADSC
tS
A ADDRESS
A1
A2
tH
A3
A4
A5
BW BWxb, a, BW BW BWE c, BW d, GW BW G E, W
CE
CE
ADV ADV
OE E O
DQx DQ
Q (A1) Single Reads
Q (A2)
D(A3) Single W rite
Q (A4)
Q (A4+1) Burst Read
Q (A4+2)
D(A5)
D(A5+1)
Burst W rite
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CY7C1360A CY7C1362A
Switching Waveforms (continued)
ZZ Mode Timing [31, 32]
CLK
ADSP
HIGH
ADSC CE1 CE2
LOW
HIGH
CE3
ZZ
tZZS
IDD
IDD(active) IDDZZ
tZZREC
I/Os Three-state
Notes: 31. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 32. I/Os are in three-state when exiting ZZ sleep mode.
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CY7C1360A CY7C1362A
Ordering Information
Speed (MHz) 225 Ordering Code CY7C1360A-225AJC CY7C1360A-225AC CY7C1360A-225BGC 200 CY7C1360A-200AJC CY7C1360A-200AC CY7C1360A-200BGC 166 CY7C1360A-166AJC CY7C1360A-166AC CY7C1360A-166BGC 150 CY7C1360A-150AJC CY7C1360A-150AC CY7C1360A-150BGC 225 CY7C1362A-225AJC CY7C1362A-225AC CY7C1362A-225BGC 200 CY7C1362A-200AJC CY7C1362A-200AC CY7C1362A-200BGC 166 CY7C1362A-166AJC CY7C1362A-166AC CY7C1362A-166BGC 150 CY7C1362A-150AJC CY7C1362A-150AC CY7C1362A-150BGC 200 CY7C1360A-200AJI CY7C1360A-200AI CY7C1360A-200BGI 166 CY7C1360A-166AJI CY7C1360A-166AI CY7C1360A-166BGI 150 CY7C1360A-150AJI CY7C1360A-150AI CY7C1360A-150BGI 200 CY7C1362A-200AJI CY7C1362A-200AI CY7C1362A-200BGI 166 CY7C1362A-166AJI CY7C1362A-166AI CY7C1362A-166BGI 150 CY7C1362A-150AJI CY7C1362A-150AI CY7C1362A-150BGI Package Name A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 Package Type 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead BGA (14 x 22 x 2.4 mm) Industrial Industrial Commercial Operating Range Commercial
Document #: 38-05258 Rev. *A
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CY7C1360A CY7C1362A
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
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CY7C1360A CY7C1362A
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4) BG119
51-85115-*A
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05258 Rev. *A
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1360A CY7C1362A
Document Title:CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Document Number: 38-05258 REV ** *A ECN No. 113846 116062 Issue Date 05/22/02 05/28/02 Orig. of Change GLC BRI Description of Change Change from Spec.: 38-00990 to 38-05258 Removed GVT part numbers from title and body of datasheet Added note 19 (pg. 19) regarding VCC on "Power On"
Document #: 38-05258 Rev. *A
Page 28 of 28

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